Sorry, but things are very slow here at BlackPundit.com. I have a major project at school due in about a week or two. With work and this project taking the majority of my free time, it is really hard for me to read, watch the news and update my site. Sorry for the inconvenience. This project that I am doing is for a VLSI course and the topic is to determine the worst-case crosstalk using ATPG. This will be an extensive C/C++ application. The test bench will be a Verilog design. I found a C Verilog parser and got it working with C, but since I need to use C++ data structures, it is really hard compiling some of the parser code with C++. If you know a little about programming, C++ is stricter on coding than C. Therefore, there are a lot of code in the parser that will compile with C and not with C++. My next step know is to try to make the hieratical Verilog test bench into a flatten test bench and write a little mini parser myself using the Standard Template Library (STL) that is provide with C++. Well, click here for the progress report if you are interested more on what this project is about.